1. Field of the Invention
The present invention relates to a video signal processing apparatus and an integrated circuit for outputting video signal data differing in resolution from input video signal data.
2. Description of Related Arts
Video signal data has a resolution determined by a pixel count in the horizontal direction and a line count in the vertical direction. The resolution of video signal data varies depending on video equipment (e.g., TV receiver, LCD or PC monitor). For this reason, video equipment incorporates a capability for converting the resolution of input video signal data as appropriate if the equipment requires video signal data which differs in resolution from input video signal data.
The capability for converting the resolution of input video signal data as appropriate can be implemented by using a field memory or a plurality of line memories.
An approach using a field memory consists in converting the resolution by writing one screenful of video signal data to the field memory at an as-is timing, reading one screenful of video signal data from the field memory at a timing different from that for writing data and performing computation for increasing or reducing the line count of video signal data as appropriate. However, this approach requires the field memory to store all the screenful of video signal data together, requiring a large-capacity memory and therefore resulting in a larger video signal processing apparatus and increased cost.
On the other hand, an approach using a plurality of line memories consists in converting the resolution by sequentially writing video signal data line by line to a plurality of line memories at an as-is timing, reading video signal data line by line from a plurality of line memories at a timing different from that for writing data and performing computation for increasing or reducing the line count of video signal data as appropriate. However, horizontal frequency for writing to individual line memories differs from that for reading from individual line memories in this approach. Additionally, the maximum time difference between writing to and reading from individual line memories is only several lines long. Therefore, timing control for writing to and reading from individual line memories requires correspondingly high accuracy, thus resulting in complex control. For example, if line memory write and read timings are reversed as a result of slight change in these timings, the screen image becomes disturbed due to loss of continuity.
For this reason, the following techniques have been proposed for preventing a reversal of line memory write and read timings.
<<Related Technique 1>>
A method for determining the pixel count in the horizontal direction of video signal data on the output side by counting a horizontal period of video signal data on the input side with a video signal data read clock on the output side, performing a specified computation for the count and the conversion rate of the resolution of video signal data in the vertical direction. This method is designed to prevent a reversal of line memory write and read timings by letting the pixel count in the horizontal direction of video signal data on the output side be uniquely related to the pixel count in the horizontal direction of video signal data on the input side.
<<Related Technique 2>>
A method for determining the video signal data read clock on the output side based on the conversion rate of the resolution in the vertical direction of video signal data by using a fixed pixel count in the horizontal direction of video signal data on the output side and configuring a PLL (Phase Locked Loop) which uses the horizontal frequency of video signal data on the input side as its reference frequency. This method is designed to prevent a reversal of line memory write and read timings by bringing the horizontal frequency of video signal data on the input side into synchronization with the video signal data read clock on the output side.
<<Related Technique 3>>
A method in which the horizontal frequency of video signal data on the input side in the related technique 2 is replaced with the vertical frequency. This method is designed to prevent a reversal of line memory write and read timings by bringing the vertical frequency of video signal data on the input side into synchronization with the video signal data read clock on the output side, that is, by bringing the horizontal frequency of video signal data on the input side substantially into synchronization with the video signal data read clock on the output side.
In the related technique 1, however, since the horizontal frequency of video signal data on the input side is not in synchronization with the video signal data read clock on the output side, the pixel count in the horizontal direction of video signal data on the output side has an error, possibly resulting in a reversal of line memory write and read timings.
In the related technique 2, the PLL does not function in the absence of the horizontal frequency of video signal data on the input side, thus making it impossible to obtain the video signal data read clock on the output side. For this reason, if no video signal data is available on the input side, means must be provided to supply a pseudo frequency equivalent to the horizontal frequency to the PLL, possibly resulting in complex control for the video signal processing apparatus.
In the related technique 3, the vertical frequency of video signal data on the input side is low for use as the PLL's reference frequency, possibly making it difficult to configure the PLL itself. In addition, the related technique 3 has the same problems as the related technique 2.